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[Other resource] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776642 | Author: 张涛 | Hits:

[Other resource] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 678583 | Author: 钟方 | Hits:

[Other resource] ddr_cntl_a_withtb

Description: arm控制FPGA的DDR测试代码，共享一下-arm control FPGA DDR test code sharing what
Platform: | Size: 2385568 | Author: yourname | Hits:

[Other resource] xapp858[1]

Description: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集 本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。 本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input / Solution Series (ISERDES) and serial output / Solution Series (O Legacy) function.
Platform: | Size: 297475 | Author: mingming | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: ddr sdram 的控制程序，lattice的，比较好用的，大家-ddr sdram control program, lattice, and relatively easy to use, and we look
Platform: | Size: 8483840 | Author: 熊熊 | Hits:

[VHDL-FPGA-Verilog] ddr_model_c3

Description: DDR仿真模型，采用erilong语言，FPGA开发DDR控制器必备-DDR simulation module verilog
Platform: | Size: 9216 | Author: 张雪松 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: DDR2内存条在FPGA中的应用,包括内部结构，时序操作和注意事项。-about DDR2 APLLICATION IN FPGA，includ inner instraction timequist and attend.
Platform: | Size: 2529280 | Author: 李 | Hits:

[Other] DDR-SDRAM--controllor-of-FPGA

Description: 本文档设计了一种FPGA控制DDR SDRAM的方法，详细介绍了控制内容。比较有参考价值。-This document is designed DDR SDRAM, a FPGA control method, detailed control content. Reference value.
Platform: | Size: 64512 | Author: 秦艳召 | Hits:

[Other] DDR-SDRAM

Description: DDR SDRAM控制器的FPGA实现-DDR SDRAM Controller with FPGA
Platform: | Size: 249856 | Author: pzf | Hits:

[VHDL-FPGA-Verilog] DDR2-design-out-of-fpga

Description: FPGA外部的ddr2设计的相关学习资料-off-fpga，ddr design
Platform: | Size: 182272 | Author: 黄志沛 | Hits:

[Software Engineering] realization-of-VGA-display-with-FPGA

Description: <用FPGA实现VGA显示> 摘要：本文介绍了一种用FPGA结合DDR SDRAM和单片机，在VGA显示器上显示字符、图形信息的方法。-The realization of VGA display with FPGA
Platform: | Size: 239616 | Author: zblinux | Hits:

[VHDL-FPGA-Verilog] DDR-SDRAM-Controller

Description: DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM Controller Using Virtex-5 FPGA Devices
Platform: | Size: 262144 | Author: 马龙 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
Platform: | Size: 4943872 | Author: 松鼠 | Hits:

[VHDL-FPGA-Verilog] RGMII_RECEIVER

Description: This module converts 4 bit DDR RGMII flow to 8 bit SDR flow, proved on Altera Cyclone 3 devices.
Platform: | Size: 2027520 | Author: serg_86 | Hits:

[VHDL-FPGA-Verilog] RGMII_TRANSMITTER

Description: This module converts 8 bit SDR flow to 4 bit DDR RGMII flow, proved on Altera Cyclone 3 devices.
Platform: | Size: 2045952 | Author: serg_86 | Hits:

[VHDL-FPGA-Verilog] ddr3_mig8

Description: fpga实现ddr数据收发测试，完整的工程，下载解压后，即可正确运行，已多次验证无误(FPGA DDR data receive and receive test, complete engineering, download and unzip, can run correctly, has been verified many times)
Platform: | Size: 16119808 | Author: 大木瓜 | Hits:

[VHDL-FPGA-Verilog] AXI-full

Description: axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)
Platform: | Size: 8192 | Author: 橙子很好吃 | Hits:

[VHDL-FPGA-Verilog] FPGA读取sd卡音频到DDR

Description: Xilinx FPGA读取sd卡音频到DDR，vivado实现
Platform: | Size: 17959013 | Author: 393975487@qq.com | Hits:

[Other] 02Kintex修炼秘籍-MIG DDR应用3缓存设计

Description: vivado下的MIG教程,适用于XILINX 7系列FPGA(MIG tutorial under vivado.)
Platform: | Size: 4861952 | Author: 城北的D1B | Hits:

[VHDL-FPGA-Verilog] S02《Artix7修炼秘籍》MIG_DDR内存应用

Description: artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)
Platform: | Size: 5444608 | Author: 北极徘徊 | Hits:
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